How SPI, I²C, UART Write to EEPROM Memory

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Deep Dive: How I2C, SPI, and UART Write to EEPROM Memory (With Bit-Level Examples)



EEPROM (Electrically Erasable Programmable Read-Only Memory) is the unsung hero of embedded systems. It bridges the gap between volatile RAM (which forgets everything when power drops) and Flash memory (which wears out quickly and requires erasing large blocks at once). EEPROM allows us to read and write data down to the individual byte level, making it perfect for storing configuration matrices, calibration coefficients, state machines, and user settings.

However, an EEPROM chip cannot think for itself. It relies entirely on serial communication protocols to receive instructions. In this comprehensive guide, we will dissect exactly how the three industry-standard protocols—I2C, SPI, and UART—perform write operations to an EEPROM, detailing the exact sequences, hex payloads, and critical timing constraints.

The Golden Rules of EEPROM Hardware

Regardless of the protocol you choose, the physical silicon inside an EEPROM operates under strict physical constraints. Understanding these two rules will save you hours of debugging:

1. The Self-Timed Internal Write Cycle ($t_{wc}$)

When a microcontroller sends data to an EEPROM, the data doesn't instantly fuse into the memory cells. It is first caught in a temporary hardware buffer. Once the microcontroller sends a "Stop", "Release", or final command packet, the EEPROM initiates its internal write cycle ($t_{wc}$).

During this period (which typically takes 3ms to 5ms), the chip uses an internal charge pump to generate high voltages (around 10V–12V) to tunnel electrons through a floating-gate transistor. Crucial Point: During this 5ms window, the EEPROM is effectively "blind" and "deaf." If you attempt to send another write or read command, the chip will completely ignore you.

2. Page Boundaries and "Roll-Over"

EEPROMs are partitioned into small physical segments called Pages (typically 8, 16, 32, or 64 bytes wide depending on the chip size). When doing a sequential block write, if your data payload crosses a page boundary, the internal address counter will roll over to the beginning of the current page, accidentally overwriting your old data instead of moving to the next page! Your software driver must manually handle these page boundaries.

1. The I2C EEPROM Write Protocol

I2C (Inter-Integrated Circuit) is a synchronous, multi-device, 2-wire bus using SDA (Serial Data) and SCL (Serial Clock) lines. Because all devices share the same wires, every transaction requires explicit device addressing.

Concrete Example: Single-Byte I2C Write

Let's map out exactly what happens when a microcontroller writes a sensor data byte of 0x55 (Binary: 01010101) into a standard 256Kbit EEPROM (like the Microchip 24LC256). We want to save this to memory address 0x00A2.

The 24LC256 has a fixed 7-bit physical hardware address template of 1010A₂A₁A₀. Assuming the hardware designer wired the external address pins $A_2, A_1, A_0$ to Ground ($0$), the chip's unique 7-bit I2C address becomes 1010000 (Hex: 0x50).

Here is the exact frame order streamed bit-by-bit over the SDA line:

Step Sequence Hex Transmitted Binary Streamed (MSB First) Bus Action / Meaning
1. Bus Alert — [START Condition] Master pulls SDA low while SCL is high.
2. Control Byte 0xA0 1 0 1 0 0 0 0 0 + [ACK] 7 bits for EEPROM ID (0x50) + Last bit 0 (Write instruction). EEPROM pulls line down for ACK.
3. Target Address (High) 0x00 0 0 0 0 0 0 0 0 + [ACK] Upper 8 bits of the internal memory location.
4. Target Address (Low) 0xA2 1 0 1 0 0 0 1 0 + [ACK] Lower 8 bits of the memory location. Pointer is now set to 0x00A2.
5. Data Payload 0x55 0 1 0 1 0 1 0 1` + [ACK] The actual data byte containing our payload. Packed into internal buffer registers.
6. Execution — [STOP Condition] SDA shifts low-to-high while SCL is high. EEPROM cuts external comms and initiates internal 5ms hardware burn.

2. The SPI EEPROM Write Protocol

SPI (Serial Peripheral Interface) is a 4-wire, high-speed architecture using SCK (Clock), MOSI (Master Out Slave In), MISO (Master In Slave Out), and CS (Chip Select). It does away with device address bytes entirely; pulling a specific chip's CS line LOW enables communication instantly.

Concrete Example: SPI Two-Step Write Sequence

Let's execute the exact same operation using an SPI EEPROM (like the Microchip 25AA256): write data byte 0x55 into memory address 0x00A2.

SPI EEPROMs utilize a hardcoded command table called opcodes to distinguish instructions. To protect against accidental write cycles caused by system voltage crashes, the chip initializes with an absolute lock state. Writing requires a deliberate, two-transaction handshaking dance.

Transaction 1: Unlock the Memory Latch (WREN Command)

Before the chip will accept data modifications, you must flag its internal Write Enable Latch (WEL) bit using the WREN opcode (0x06).

  1. Master drives the CS line LOW to awake this specific chip.
  2. Master streams out the 8-bit instruction byte 0x06 (Binary: 00000110) over the MOSI line.
  3. Master drives the CS line HIGH. Warning: This step is mandatory! The chip's state-machine engine processes internal register locks specifically on the rising edge of the Chip Select pin.

Transaction 2: Stream the Target Location and Payload

With the physical register unlocked, the microcontroller immediately addresses the target space:

  1. Master drives the CS line LOW again.
  2. Master transmits the specific WRITE command opcode: 0x02 (Binary: 00000010). This primes the EEPROM's input decoder.
  3. Master transmits the high byte of our destination address: 0x00.
  4. Master transmits the low byte of our destination address: 0xA2. The address pointer is now internally locked onto cell index 0x00A2.
  5. Master transmits the data payload: 0x55.
  6. Master drives the CS line HIGH. This rising edge signals that the transaction is finalized, kicking off the 5ms hardware burn cycle inside the chip.

3. The UART EEPROM Write Protocol (Asynchronous Serial)

UART (Universal Asynchronous Receiver-Transmitter) is a 2-wire protocol using dedicated TX (Transmit) and RX (Receive) lines. Unlike I2C and SPI, UART is asynchronous—there is no shared clock line ($SCL$ or $SCK$) coordinating the bits. Instead, both devices must be pre-configured to run at the exact same speed (Baud Rate, e.g., 9600 or 115200 bps).

Pure bare-die EEPROMs rarely feature a raw UART interface because asynchronous timing requires complex internal hardware oscillators. Instead, UART communication is standard when using "Smart" EEPROMs, serial memory modules, or coprocessors that use a standard byte-packet framework.

Concrete Example: Packetized UART Write

Because there is no hardware Chip Select line or Start/Stop bus conditions to isolate a frame, a UART write operation relies entirely on a software-defined packet framework. To perform the same write of data 0x55 to memory address 0x00A2, the master device transmits a structured multi-byte command string over its TX line:

Byte Position Hex Transmitted UART Hardware Framing (8N1 Layout) Functional Meaning
Byte 1: Command 0x57 [Start Bit 0] + 11101010 (LSB First) + [Stop Bit 1] ASCII character 'W' indicating a Write Command.
Byte 2: Addr High 0x00 [Start Bit 0] + 00000000 + [Stop Bit 1] Upper 8 bits of target memory space.
Byte 3: Addr Low 0xA2 [Start Bit 0] + 01000101 (LSB First) + [Stop Bit 1] Lower 8 bits of target memory space. Target locked to 0x00A2.
Byte 4: Data 0x55 [Start Bit 0] + 10101010 (LSB First) + [Stop Bit 1] The actual data byte payload to be burned.
Byte 5: Checksum 0xF9 [Start Bit 0] + 10011111 (LSB First) + [Stop Bit 1] Simple XOR or summation validation byte to ensure zero data line corruption occurred.
The Hidden Cost of UART: Notice the Start and Stop bits wrapped around every single hardware byte block. Because there is no external clock track coordinating data lines, the UART hardware must waste 2 bits of raw bus overhead per byte just to align the receiver's sampling engine.

Protocol Comparison: I2C vs. SPI vs. UART

Metric I2C EEPROM SPI EEPROM UART Memory Modules
Pins Required 2 (SDA, SCL) 4 (MOSI, MISO, SCK, CS) 2 (TX, RX)
Clocking Synchronous (Shared Clock Line) Synchronous (Shared Clock Line) Asynchronous (No Shared Clock)
Hardware Speed 100 kHz – 1 MHz Fastest (10 MHz – 20 MHz+) Slowest (Typically 9600 – 115200 bps)
Byte Order Most Significant Bit First (MSB) Most Significant Bit First (MSB) Least Significant Bit First (LSB)
Data Verification Hardware ACK/NACK bit per byte Read back status register manually Software Packet Checksum / Parity Bit

Summary: When to use which?

  • Choose I2C if: You have highly limited microchip pin structures but want to daisy-chain multiple local onboard IC components together safely.
  • Choose SPI if: You are logging high-frequency sensor readings down onto the storage layout where raw bus speeds and minimal overhead are key.
  • Choose UART if: You are communicating long-distance over complex board layouts (or wire harnesses) to a dedicated peripheral storage module, avoiding cross-talk vulnerabilities common with fast synchronous clock lines.

Which of these serial architectures fits your current design parameters? Drop your hardware setups or question marks below in the comment stream!

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